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56f800 16-bit digital signal controllers freescale.com 56f801 data sheet preliminary technical data DSP56F801 rev. 16 01/2007

56f801 technical data, rev. 16 freescale semiconductor 3 ? up to 30 mips operation at 60mhz core frequency ? up to 40 mips operation at 80mhz core frequency ? dsp and mcu functionality in a unified, c-efficient architecture ? mcu-friendly instruction set supports both dsp and controller functions: mac, bit manipulation unit, 14 addressing modes ? hardware do and rep loops ? 6-channel pwm module ? two 4-channel, 12-bit adcs ? serial communicatio ns interface (sci) ? serial peripheral interface (spi) ?8k 16-bit words (16kb) program flash ?1k 16-bit words (2kb) program ram ?2k 16-bit words (4kb) data flash ?1k 16-bit words (2kb) data ram ?2k 16-bit words (4kb) boot flash ? general purpose quad timer ? jtag/once tm port for debugging ? on-chip relaxation oscillator ? 11 shared gpio ? 48-pin lqfp package 56f801 general description 56f801 block diagram jtag/ once port digital reg analog reg low voltage supervisor program controller and hardware looping unit data alu 16 x 16 + 36 36-bit mac three 16-bit input registers two 36-bit accumulators address generation unit bit manipulation unit pll clock gen or optional internal relaxation osc. 16-bit 56800 core pab pdb xdb2 cgdb xab1 xab2 gpiob3/xtal gpiob2/extal interrupt controls ipbb controls ipbus bridge (ipbb) module controls address bus [8:0] data bus [15:0] cop reset reset irqa applica- tion-specific memory & peripherals interrupt controller program memory 8188 x 16 flash 1024 x 16 sram boot flash 2048 x 16 flash data memory 2048 x 16 flash 1024 x 16 sram cop/ watchdog spi or gpio sci0 or gpio quad timer d or gpio quad timer c a/d1 a/d2 adc 4 2 3 4 4 6 pwm outputs fault input pwma 16 16 vcapc v dd v ss v dda v ssa 6 24 5* ? ? ? ? ? ? ? ? vref * includes tcs pin which is reserv ed for factory use and is tied to vss
56f801 technical data, rev. 16 4 freescale semiconductor part 1 overview 1.1 56f801 features 1.1.1 digital signal processing core ? efficient 16-bit 56800 family controller engine with dual harvard architecture ? as many as 40 million instructions pe r second (mips) at 80mhz core frequency ? single-cycle 16 16-bit parallel multiplier-accumulator (mac) ? two 36-bit accumulators including extension bits ? 16-bit bidirectional barrel shifter ? parallel instruction set with un ique processor addressing modes ? hardware do and rep loops ? three internal address buses and one external address bus ? four internal data buses and one external data bus ? instruction set supports both dsp and controller functions ? controller style addressing modes and instructions for compact code ? efficient c compiler and local variable support ? software subroutine and interrupt stac k with depth limited only by memory ? jtag/once debug programming interface 1.1.2 memory ? harvard architecture permits as many as three simultaneous accesses to program and data memory ? on-chip memory including a low-cost, high-volume flash solution ?8k 16 bit words of program flash ?1k 16-bit words of program ram ?2k 16-bit words of data flash ?1k 16-bit words of data ram ?2k 16-bit words of boot flash ? programmable boot flash supports customized boot co de and field upgrades of stored code through a variety of interfaces (jtag, spi) 1.1.3 peripheral circuits for 56f801 ? pulse width modulator (pwm) with six pwm outputs, tw o fault inputs, fault-tolera nt design with deadtime insertion; supports both ce nter- and edge-aligned modes ? two 12-bit, analog-to-digital conv erters (adcs), which support two simultaneous conversions with two 4-multiplexed inputs; adc and pw m modules can be synchronized ? general purpose quad timer: timer d with three pins (or three additional gpio lines) ? serial communication interface (sci) with two pins (or two additional gpio lines) ? serial peripheral interface (spi) with configurab le four-pin port (or four additional gpio lines)
56f801 description 56f801 technical data, rev. 16 freescale semiconductor 5 ? eleven multiplexed general purpose i/o (gpio) pins ? computer-operating properly (cop) watchdog timer ? one dedicated external interrupt pin ? external reset pin for hardware reset ? jtag/on-chip emulation (once?) for unobtrusi ve, processor speed-ind ependent debugging ? software-programmable, phase locked loop-based frequency synthesizer for the controller core clock ? oscillator flexibility between either an external crys tal oscillator or an on-chi p relaxation oscillator for lower system cost and tw o additional gpio lines 1.1.4 energy information ? fabricated in high-density cmos with 5v-tolerant, ttl-compatible digital inputs ? uses a single 3.3v power supply ? on-chip regulators for digital and analog circuitry to lower cost and reduce noise ? wait and stop modes available 1.2 56f801 description the 56f801 is a member of the 56800 core-based family of processors. it combines, on a single chip, the processing power of a dsp and the func tionality of a microcont roller with a flexible set of peripherals to create an extremely cost-effective solution. because of its low cost , configuration flexibility, and compact program code , the 56f801 is well-sui ted for many applications . the 56f801 includes many peripherals that are especially usef ul for applications such as motion control, smart appliances, steppers, encoders, tachometers, limit sw itches, power supply a nd control, automotive control, engine management, noise suppression, remo te utility metering, a nd industrial control for power, lighting, and automation. the 56800 core is based on a harvard-style architectur e consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. the microprocessor- style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both dsp and mcu applications. the instru ction set is also highly efficient for c compilers to enable rapid development of optimized control applications. the 56f801 supports program executi on from either internal or extern al memories. two data operands can be accessed from the on-chip data ram per instruct ion cycle. the 56f801 also provides one external dedicated interrupt lines and up to 11 general purpos e input/output (gpio) line s, depending on peripheral configuration. the 56f801 controller includes 8k wo rds (16-bit) of program flash and 2k words of data flash (each programmable through the jtag port) with 1k words of both program and data ram. a total of 2k words of boot flash is incorporat ed for easy customer-inclusion of field-programmable software routines that can be used to program the ma in program and data flash memory ar eas. both program and data flash memories can be independently bulk er ased or erased in page sizes of 256 words. the boot flash memory can also be either bulk or page erased.
56f801 technical data, rev. 16 6 freescale semiconductor a key application-specific feature of the 56f801 is the inclusion of a puls e width modulator (pwm) module. this modules incorporat es six complementary, individuall y programmable pwm signal outputs to enhance motor control functi onality. complementary operation permits programmable dead-time insertion, and separate top and bot tom output polarity control. the up- counter value is programmable to support a continuously variable pwm frequency. both edge- and center -aligned synchron ous pulse width control (0% to 100% modulation) are supported. the devi ce is capable of controlling most motor types: acim (ac induction motors), both bdc and bldc (brush and brushl ess dc motors), srm and vrm (switched and variable reluctance motors), and stepper motors. the pwms incorporate fault protection and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard opto-isolators. a ?smoke-inhibit?, wr ite-once protection feature for key parameters is also included. the pwm is double-buffered and includes inte rrupt control to permit integral reload rates to be programmable from 1 to 16. the pwm modules provide a refere nce output to synchronize the analog-to-digital converters. the 56f801 incorporates an 8 input, 12-bit analog-to-d igital converter (adc). a full set of standard programmable peripherals is provide d that include a serial communicat ions interface (sci), a serial peripheral interface (spi), and two quad timers. any of these interfaces can be used as general-purpose input/outputs (gpio) if that functio n is not required. an on-chip relaxa tion oscillator provides flexibility in the choice of either on-chip or externally supplied frequency reference for chip timing operations. application code is used to sel ect which source is to be used. 1.3 state of the art development environment ? processor expert tm (pe) provides a rapid application design (rad) tool that combines easy-to-use component-based software ap plication creation with an expert knowledge system. ? the code warrior integrated development environm ent is a sophisticated to ol for code navigation, compiling, and debugging. a complete set of eval uation modules (evms) and development system cards will support concurrent engineering. together, pe, code warrior and evms create a complete, scalable tools solution for easy, fast, and efficient development.
product documentation 56f801 technical data, rev. 16 freescale semiconductor 7 1.4 product documentation the four documents listed in table 1-1 are required for a complete desc ription and proper design with the 56f801. documentation is available from local frees cale distributors, freescale semiconductor sales offices, freescale literature dist ribution centers, or online at www.freescale.com . 1.5 data sheet conventions this data sheet uses the following conventions: table 1-1 56f801 chip documentation topic description order number 56800e family manual detailed description of the 56800 family architecture, and 16-bit core processor and the instruction set 56800efm DSP56F801/803/805/807 user?s manual detailed description of memory, peripherals, and interfaces of the 56f801, 56f803, 56f805, and 56f807 DSP56F801-7um 56f801 technical data sheet electrical and timing specific ations, pin descriptions, and package descriptions (this document) DSP56F801 56f801 errata details any chip issues that might be present 56f801e overbar this is used to indicate a signal that is active when pulled low. for example, the reset pin is active when low. ?asserted? a high true (active high) signal is high or a low true (active low) signal is low. ?deasserted? a high true (active high) signal is low or a low true (active low) signal is high. examples: signal/symbol logic state signal state voltage 1 1. values for v il , v ol , v ih , and v oh are defined by individual product specifications. pin true asserted v il /v ol pin false deasserted v ih /v oh pin true asserted v ih /v oh pin false deasserted v il /v ol
56f801 technical data, rev. 16 8 freescale semiconductor part 2 signal/connection descriptions 2.1 introduction the input and output signals of the 56f801 are organized into functional groups, as shown in table 2-1 and as illustrated in figure 2-1 . in table 2-2 through table 2-12 , each table row describes the signal or signals present on a pin. table 2-1 functional group pin allocations functional group number of pins detailed description power (v dd or v dda )5 table 2-2 ground (v ss or v ssa )6 table 2-3 supply capacitors 2 table 2-4 pll and clock 2 table 2-5 interrupt and program control 2 table 2-6 pulse width modulator (pwm) port 7 table 2-7 serial peripheral interface (spi) port 1 1. alternately, gpio pins 4 table 2-8 serial communications interface (sci) port 1 2 table 2-9 analog-to-digital converter (adc) port 9 table 2-10 quad timer module port 3 table 2-11 jtag/on-chip emulation (once) 6 table 2-12
introduction 56f801 technical data, rev. 16 freescale semiconductor 9 figure 2-1 56f801 signals iden tified by functional group 1 1. alternate pin functionality is shown in parenthesis. 56f801 power port ground port power port ground port pll and clock or gpio sci0 port or gpio v dd v ss v dda v ssa vcapc extal (gpiob2) xtal (gpiob3) tck tms tdi tdo trst de jtag/once ? port pwma0-5 faulta0 sclk (gpiob4) mosi (gpiob5) miso (gpiob6) ss (gpiob7) txd0 (gpiob0) rxd0 (gpiob1) ana0-7 vref td0-2 (gpioa0-2) irqa reset quad timer d or gpio adca port other supply port 4 5* 1 1 2 1 1 1 1 1 1 1 1 interrupt/ program control 6 1 1 1 1 1 1 1 8 1 3 1 1 spi port or gpio * includes tcs pin which is reserv ed for factory use and is tied to vss
56f801 technical data, rev. 16 10 freescale semiconductor 2.2 power and ground signals 2.3 clock and phase locked loop signals table 2-2 power inputs no. of pins signal na me signal description 4 v dd power ?these pins provide power to the internal structures of the chip, and should all be attached to v dd. 1 v dda analog power ?this pin is a dedicated power pin for the analog portion of the chip and should be connected to a low noise 3.3v supply. table 2-3 grounds no. of pins signal name signal description 4 v ss gnd ?these pins provide grounding for the internal structures of the chip, and should all be attached to v ss. 1 v ssa analog ground ?this pin supplies an analog ground. 1 tcs tcs ?this schmitt pin is reserved for factory use and must be tied to v ss for normal use. in block diagrams, this pin is considered an additional v ss. table 2-4 supply ca pacitors and vpp no. of pins signal name signal type state during reset signal description 2 vcapc supply supply vcapc ?connect each pin to a 2.2 for greater bypass capacitor in order to bypass the core logic voltage regulator (required for proper chip operation). for more in formation, refer to section 5.2 . table 2-5 pll and clock no. of pins signal name signal type state during reset signal description 1 extal gpiob2 input input/ output input input external crystal oscillator input ?this input should be connected to an 8mhz external crystal or ceramic resonator. for more information, please refer to section 3.5 . port b gpio ?this multiplexed pin is a general purpose i/o (gpio) pin that can be programmed as an input or output pin. this i/o can be utilized when using the on-chip relaxation oscillator so the extal pin is not needed.
interrupt and program control signals 56f801 technical data, rev. 16 freescale semiconductor 11 2.4 interrupt and program control signals 2.5 pulse width modulator (pwm) signals 1 xtal gpiob3 output input/ output chip- driven input crystal oscillator output ?this output should be connected to an 8mhz external crystal or ceramic resonator. for more information, please refer to section 3.5 . this pin can also be connected to an external clock source. for more information, please refer to section 3.5.3 . port b gpio ?this multiplexed pin is a general purpose i/o (gpio) pin that can be programmed as an input or output pin. this i/o can be utilized when using the on-chip relaxation oscillator so the xtal pin is not needed. table 2-6 interrupt and program control signals no. of pins signal name signal type state during reset signal description 1 irqa input (schmitt) input external interru pt request a ?the irqa input is a synchronized external interrupt request that indicates that an external device is requesting service. it can be programmed to be level-sensitive or negative-edge- triggered. 1 reset input (schmitt) input reset ?this input is a direct hardware reset on the processor. when reset is asserted low, the controller is initialized and placed in the reset state. a schmitt trigger input is used for noise immunity. when the reset pin is deasserted, the initial chip operating mode is latched from the extboot pin. the internal reset signal will be deasserted synchronous with the internal clocks, after a fixed number of internal clocks. to ensure complete hardware reset, reset and trst should be asserted together. the only exception occurs in a debugging environment when a hardware device reset is required and it is necessary not to reset the once/jtag module. in this case, assert reset , but do not assert trst . table 2-7 pulse width m odulator (pwma) signals no. of pins signal name signal type state during reset signal description 6 pwma0-5 output tri-stated pwma0-5 ? these are six pwma output pins. 1 faulta0 input (schmitt) input faulta0 ? this fault input pin is used for disabling selected pwma outputs in cases where fault conditions originate off-chip. table 2-5 pll and clock (continued) no. of pins signal name signal type state during reset signal description
56f801 technical data, rev. 16 12 freescale semiconductor 2.6 serial peripheral interface (spi) signals table 2-8 serial periphera l interface (spi) signals no. of pins signal name signal type state during reset signal description 1 miso gpiob6 input/output input/output input input spi master in/slave out (miso) ?this serial data pin is an input to a master device and an output from a slave device. the miso line of a slave device is placed in the high-impedance state if the slave device is not selected. port e gpio ?this pin is a general purpose i/o (gpio) pin that can be individually programmed as input or output pin. after reset, the default state is miso. 1 mosi gpiob5 input/output input/output input input spi master out/slave in (mosi) ?this serial data pin is an output from a master device and an input to a slave device. the master device places data on the mosi line a half-cycle before the clock edge that the slave device uses to latch the data. port e gpio ?this pin is a general purpose i/o (gpio) pin that can be individually programmed as input or output pin. after reset, the default state is mosi. 1 sclk gpiob4 input/output input/output input input spi serial clock ?in master mode, this pin serves as an output, clocking slaved listeners. in slave mode, this pin serves as the data clock input. port e gpio ?this pin is a general purpose i/o (gpio) pin that can be individually programmed as an input or output pin. after reset, the default state is sclk. 1 ss gpiob7 input input/output input input spi slave select ?in master mode, this pin is used to arbitrate multiple masters. in slave mode, th is pin is used to select the slave. port e gpio ?this pin is a general purpose i/o (gpio) pin that can be individually programmed as an input or output pin. after reset, the default state is ss .
serial communications interface (sci) signals 56f801 technical data, rev. 16 freescale semiconductor 13 2.7 serial communications interface (sci) signals 2.8 analog-to-digital converter (adc) signals 2.9 quad timer module signals table 2-9 serial communicati ons interface (sci0) signals no. of pins signal name signal type state during reset signal description 1 txd0 gpiob0 output input/output input input transmit data (txd0) ?sci0 transmit data output port b gpio ?this pin is a general purpose i/o (gpio) pin that can be individually programmed as an input or output pin. after reset, the default state is sci output. 1 rxd0 gpiob1 input input/output input input receive data (rxd0) ?sci0 receive data input port b gpio ?this pin is a general purpose i/o (gpio) pin that can be individually programmed as an input or output pin. after reset, the default state is sci input. table 2-10 analog to di gital converter signals no. of pins signal name signal type state during reset signal description 4 ana0-3 input input ana0-3 ?analog inputs to adc, channel 1 4 ana4-7 input input ana4-7 ?analog inputs to adc, channel 2 1 vref input input vref ?analog reference voltage for adc. must be set to v dda -0.3v for optimal performance. table 2-11 quad timer module signals no. of pins signal name signal type state during reset signal description 3 td0-2 gpioa0-2 input/output input/output input input td0-2 ?timer d channel 0-2 port a gpio ?this pin is a general purpose i/o (gpio) pin that can be individually programmed as an input or output pin. after reset, the default state is the quad timer input.
56f801 technical data, rev. 16 14 freescale semiconductor 2.10 jtag/once part 3 specifications 3.1 general characteristics the 56f801 is fabricated in high-density cmos with 5-volt tolera nt ttl-compatible di gital inputs. the term ?5-volt tolerant? refe rs to the capability of an i/o pin, bu ilt on a 3.3v compatib le process technology, to withstand a voltage up to 5.5v without damaging the devi ce. many systems have a mixture of devices designed for 3.3v and 5v power suppl ies. in such systems, a bus ma y carry both 3.3v and 5v- compatible i/o voltage levels (a standard 3.3v i/o is designed to rece ive a maximum voltage of 3.3v 10% during normal operation without causing damage ). this 5v-tolerant capability therefore offers the power savings of 3.3v i/o levels while being able to receive 5v levels wi thout being damaged. absolute maximum ratings given in table 3-1 are stress ratings only, and functional operation at the maximum is not guaranteed. stress beyond these ratings may affect device reliability or cause permanent damage to the device. table 2-12 jtag/on-chip em ulation (once) signals no. of pins signal name signal type state during reset signal description 1 tck input (schmitt) input, pulled low internally test clock input ?this input pin provides a gated clock to synchronize the test logic and shift serial data to the jtag/once port. the pin is connected internally to a pull-down resistor. 1 tms input (schmitt) input, pulled high internally test mode select input ?this input pin is used to sequence the jtag tap controller?s state machine. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. note: always tie the tms pin to v dd through a 2.2k resistor. 1 tdi input (schmitt) input, pulled high internally test data input ?this input pin provides a serial input data stream to the jtag/once port. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. 1 tdo output tri-stated test data output ?this tri-statable output pin provides a serial output data stream from the jtag/once port. it is driven in the shift-ir and shift-dr controller states, and changes on the falling edge of tck. 1 trst input (schmitt) input, pulled high internally test reset ?as an input, a low signal on this pin provides a reset signal to the jtag tap controller. to ensure complete hardware reset, trst should be asserted whenever reset is asserted. the only exception occurs in a debugging environment when a hardware device reset is required and it is necessary not to reset the once/jtag module. in this case, assert reset , but do not assert trst . note: for normal operation, connect trst directly to v ss . if the design is to be used in a debugging environment, trst may be tied to v ss through a 1k resistor. 1 de output output debug event ?de provides a low pulse on recognized debug events.
general characteristics 56f801 technical data, rev. 16 freescale semiconductor 15 the 56f801 dc and ac electrical sp ecifications are prelim inary and are from de sign simulations. these specifications may not be fully tested or guaranteed at this early stage of the product life cycle. finalized specifications will be published af ter complete characterization a nd device qualificat ions have been completed. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. table 3-1 absolute maximum ratings characteristic symbol min max unit supply voltage v dd v ss ? 0.3 v ss + 4.0 v all other input voltages, excluding analog inputs v in v ss ? 0.3 v ss + 5.5v v voltage difference v dd to v dda v dd - 0.3 0.3 v voltage difference v ss to v ssa v ss - 0.3 0.3 v analog inputs ana0-7 and vref v in v ssa ? 0.3 v dda + 0.3 v analog inputs extal, xtal v in v ssa ? 0.3 v ssa + 3.0 v current drain per pin excluding v dd , v ss , & pwm ouputs i ? 10 ma table 3-2 recommended operating conditions characteristic symbol min typ max unit supply voltage, digital v dd 3.0 3.3 3.6 v supply voltage, analog v dda 3.0 3.3 3.6 v voltage difference v dd to v dda v dd -0.1 - 0.1 v voltage difference v ss to v ssa v ss -0.1 - 0.1 v adc reference voltage 1 1. vref must be 0.3 below v dda . vref 2.7 ? 3.3v v ambient operating temperature t a ?40 ? 85 c
56f801 technical data, rev. 16 16 freescale semiconductor notes: 1. theta-ja determined on 2s2p test boards is frequently lower than would be observed in an application. determined on 2s2p thermal test board. 2. junction to ambient therma l resistance, theta-ja ( r ja ) was simulated to be equivalent to the jedec specification jesd51-2 in a horizontal configuration in natural convection. theta-ja was also simulated on a thermal test board with two internal planes (2s2p where s is the number of signal layers and p is the number of planes) per jesd51-6 and jesd51-7. the correct name for theta-ja for forced convection or with the non-single layer boards is theta-jma. 3. junction to case therma l resistance, theta-jc (r jc ), was simulated to be equivalent to the measured values using the cold plate techniqu e with the cold plate temperature used as the "case" temperature. the basic cold plate measurement technique is described by mil-std 883d, method 1012.1. this is the correct thermal metric to use to calculate thermal performance wh en the package is being used with a heat sink. 4. thermal characterization parameter, psi-jt ( jt ), is the "resistance" from junction to reference point thermocouple on top center of case as defined in jesd51-2. jt is a useful value to use to estimate junction temperature in steady stat e customer environments. 5. junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temper ature, air flow, power dissipation of other components on the board, and board thermal resistance. 6. see section 5.1 from more details on thermal design considerations. 7. tj = junction temperature ta = ambient temperature table 3-3 thermal characteristics 6 characteristic comments symbol value unit notes 48-pin lqfp junction to ambient natural convection r ja 50.6 c/w 2 junction to ambient (@1m/sec) r jma 47.4 c/w 2 junction to ambient natural convection four layer board (2s2p) r jma (2s2p) 39.1 c/w 1,2 junction to ambient (@1m/sec) four layer board (2s2p) r jma 37.9 c/w 1,2 junction to case r jc 17.3 c/w 3 junction to center of case jt 1.2 c/w 4, 5 i/o pin power dissipation p i/o user determined w power dissipation p d p d = (i dd x v dd + p i/o )w junction to center of case p dmax (tj - ta) /r ja w7
dc electrical characteristics 56f801 technical data, rev. 16 freescale semiconductor 17 3.2 dc electrical characteristics table 3-4 dc electr ical characteristics operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6v, t a = ?40 to +85 c, c l 50pf characteristic symbol min typ max unit input high voltage (xtal/extal) v ihc 2.25 ? 2.75 v input low voltage (xtal/extal) v ilc 0?0.5v input high voltage [gpiob(2:3)] 1 v ih[gpiob(2:3)] 2.0 ? 3.6 v input low voltage [gpiob(2:3)] 1 v il[gpiob(2:3)] -0.3 ? 0.8 v input high voltage (schmitt trigger inputs) 2 v ihs 2.2 ? 5.5 v input low voltage (schmitt trigger inputs) 2 v ils -0.3 ? 0.8 v input high voltage (all other digital inputs) v ih 2.0 ? 5.5 v input low voltage (all other digital inputs) v il -0.3 ? 0.8 v input current high (pullup/pulldown resistors disabled, v in =v dd )i ih -1 ? 1 a input current low (pullup/pu lldown resistors disabled, v in =v ss )i il -1 ? 1 a input current high (with pullup resistor, v in =v dd )i ihpu -1 ? 1 a input current low (with pullup resistor, v in =v ss )i ilpu -210 ? -50 a input current high (with pulldown resistor, v in =v dd )i ihpd 20 ? 180 a input current low (with pulldown resistor, v in =v ss )i ilpd -1 ? 1 a nominal pullup or pulldown resistor value r pu , r pd 30 k output tri-state current low i ozl -10 ? 10 a output tri-state current high i ozh -10 ? 10 a input current high (analog inputs, v in =v dda ) 3 i iha -15 ? 15 a input current low (analog inputs, v in =v ssa ) 3 i ila -15 ? 15 a output high voltage (at i oh )v oh v dd ? 0.7 ? ? v output low voltage (at i ol )v ol ??0.4v output source current i oh 4??ma output sink current i ol 4??ma pwm pin output source current 4 i ohp 10 ? ? ma pwm pin output sink current 5 i olp 16 ? ? ma input capacitance c in ?8?pf output capacitance c out ?12?pf
56f801 technical data, rev. 16 18 freescale semiconductor v dd supply current i ddt 6 run 7 (80mhz operation) ?120130ma run 7 (60mhz operation) ?102111ma wait 8 ?96102ma stop ?6270ma low voltage interrupt, external power supply 9 v eio 2.4 2.7 3.0 v low voltage interrupt, internal power supply 10 v eic 2.0 2.2 2.4 v power on reset 11 v por ?1.72.0v 1. since the gpiob[2:3] signals are shared with the xtal/e xtal function, these inputs are not 5.5 volt tolerant. 2. schmitt trigger inputs are: faulta0, irqa , reset , tcs, tck, tms, tdi, and trst . 3. analog inputs are: ana[0:7], xtal and extal. specification assumes adc is not sampling. 4. pwm pin output source current measured with 50% duty cycle. 5. pwm pin output sink current measured with 50% duty cycle. 6. i ddt = i dd + i dda (total supply current for v dd + v dda ) 7. run (operating) i dd measured using 8mhz clock source . all inputs 0.2v from rail; outputs unloaded. all ports configured as inputs; measured with all modules enabled. 8. wait i dd measured using external square wave clock source (f osc = 8mhz) into xtal; all inputs 0.2v from rail; no dc loads; less than 50pf on all outputs. c l = 20pf on extal; all ports configured as input s; extal capacitance linearly affects wait i dd ; measured with pll enabled. 9. this low voltage interrupt monitors the v dda external power supply. v dda is generally connected to the same potential as v dd via separate traces. if v dda drops below v eio , an interrupt is generated. functionalit y of the device is guaranteed under transient conditions when v dda > v eio (between the minimum specified v dd and the point when the v eio interrupt is generated). 10. this low voltage interrupt monitors the internally regulated core power supply. if the output from the internal voltage is r egulator drops below v eic , an interrupt is generated. since the core logic supply is internally regulated, this interrupt will not be generated unless the external power supply drops bel ow the minimum specified value (3.0v). 11. power ? on reset occurs whenever the internally regulated 2.5v digita l supply drops below 1.5v typical. while power is ramping up, this signal remains active for as long as the internal 2.5v is below 1.5v typical no matter how long the ramp up rate is. t he internally regulated voltage is typically 100 mv less than v dd during ramp up until 2.5v is reached, at which time it self regulates. table 3-4 dc electrical characteristics (continued) operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6v, t a = ?40 to +85 c, c l 50pf characteristic symbol min typ max unit
ac electrical characteristics 56f801 technical data, rev. 16 freescale semiconductor 19 figure 3-1 maximum r un idd vs. frequency (see note 7. in table 3-15 ) 3.3 ac electrical characteristics timing waveforms in section 3.3 are tested using the v il and v ih levels specified in the dc characteristics table. in figure 3-2 the levels of v ih and v il for an input signal are shown. figure 3-2 input signal measurement references figure 3-3 shows the definitions of the following signal states: ? active state, when a bus or signal is driven, and enters a low impedance state. ? tri-stated, when a bus or signal is placed in a high impedance state. ? data valid state, when a signal level has reached v ol or v oh. ? data invalid state, when a signal level is in transition between v ol and v oh. 0 40 80 120 160 10 20 30 40 50 60 70 80 freq. (mhz) idd (ma) idd digital idd analog idd total v ih v il fall time input signal note: the midpoint is v il + (v ih ? v il )/2. midpoint1 low high 90% 50% 10% rise time
56f801 technical data, rev. 16 20 freescale semiconductor figure 3-3 signal states 3.4 flash memory characteristics table 3-5 flash memory truth table mode xe 1 1. x address enable, all rows are disabled when xe = 0 ye 2 2. y address enable, ymux is disabled when ye = 0 se 3 3. sense amplifier enable oe 4 4. output enable, tri-state flash data out bus when oe = 0 prog 5 5. defines program cycle erase 6 6. defines erase cycle mas1 7 7. defines mass erase cyc le, erase whole block nvstr 8 8. defines non-volatile store cycle standby l l l l l l l l read hhhh l l l l word program h h l l h l l h page erase h l l l l h l h mass erase h l l l l h h h table 3-6 ifren truth table mode ifren = 1 ifren = 0 read read information block read main memory block word program program information block program main memory block page erase erase information block erase main memory block mass erase erase both block e rase main memory block data invalid state data1 data2 valid data tri-stated data3 valid data2 data3 data1 valid data active data active
flash memory characteristics 56f801 technical data, rev. 16 freescale semiconductor 21 table 3-7 flash timing parameters operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6v, t a = ?40 to +85 c, c l 50pf characteristic symbol min typ max unit figure program time t prog* 20 ? ? us figure 3-4 erase time t erase* 20 ? ? ms figure 3-5 mass erase time t me* 100 ? ? ms figure 3-6 endurance 1 1. one cycle is equal to an erase program and read. e cyc 10,000 20,000 ? cycles data retention 1 d ret 10 30 ? years the following parameters should only be used in the manual word programming mode prog/erase to nvstr set up time t nvs* ?5?us figure 3-4 , figure 3-5 , figure 3-6 nvstr hold time t nvh* ?5?us figure 3-4 , figure 3-5 nvstr hold time (mass erase) t nvh1* ?100?us figure 3-6 nvstr to program set up time t pgs* ?10?us figure 3-4 recovery time t rcv* ?1?us figure 3-4 , figure 3-5 , figure 3-6 cumulative program hv period 2 2. thv is the cumulative high voltage programming time to the same row before next erase. the same address cannot be programmed twice before next erase. t hv ?3?ms figure 3-4 program hold time 3 3. parameters are guaranteed by design in smart pr ogramming mode and must be one cycle or greater. *the flash interface unit provides registers for the control of these parameters. t pgh ??? figure 3-4 address/data set up time 3 t ads ??? figure 3-4 address/data hold time 3 t adh ??? figure 3-4
56f801 technical data, rev. 16 22 freescale semiconductor figure 3-4 flash program cycle figure 3-5 flash erase cycle xadr yadr ye din prog nvstr tnvs tpgs tadh tprog tads tpgh tnvh trcv thv ifren xe xadr ye=se=oe=mas1=0 erase nvstr tnvs tnvh trcv terase ifren xe
external clock operation 56f801 technical data, rev. 16 freescale semiconductor 23 figure 3-6 flash ma ss erase cycle 3.5 external clock operation the 56f801 device clock is derived from either 1) an internal crystal oscillator circuit working in conjunction with an external crystal, 2) an external frequenc y source, or 3) an on-ch ip relaxation oscillator. to generate a reference frequency us ing the internal crystal oscillator circuit, a reference crystal external to the chip must be connected between the extal and xtal pins. paragraphs 3.5.1 and 3.5.4 describe these methods of clocking. whichever type of clock derivati on is used provides a reference signal to a phase-locked loop (pll) within th e 56f801. in turn, the pll generates a master referenc e frequency that determines the speed at which chip operations occur. application code can be set to cha nge the frequency source between the relaxation oscillator and crystal oscillator or external source, and power down the relaxation os cillator if desired. se lection of which clock is used is determined by setting the precs bit in the pllcr (phase-locked loop control register) word (bit 2). if the bit is set to 1, the external crystal oscillat or circuit is selected. if th e bit is set to 0, the internal relaxation oscillator is se lected, and this is the default value of the bit when power is first applied. 3.5.1 crystal oscillator the internal oscillator is also designed to interfac e with a parallel-resonant crystal resonator in the frequency range specified fo r the external crystal in table 3-10 . figure 3-7 shows a recommended crystal oscillator circuit. follow the crys tal supplier?s recommendations when selecting a crystal, since crystal parameters determine the component values required to provide maximu m stability and reliable start-up. the crystal and associated compone nts should be mounted as close as possible to the extal and xtal pins to minimize output di stortion and start-up stabi lization time. the internal 56f80x oscillator circuitry xadr ye=se=oe=0 erase nvstr tnvs tnvh1 trcv tme mas1 ifren xe
56f801 technical data, rev. 16 24 freescale semiconductor is designed to have no ex ternal load capacitors present. as shown in figure 3-8 no external load capacitors should be used. the 56f80x components internally are modeled as a pa rallel resonant oscillator circuit to provide a capacitive load on each of the osci llator pins (xtal and extal) of 10pf to 13pf over temperature and process variations. using a typical value of internal capacitance on these pins of 12pf and a value of 3pf as a typical circuit board trace capaci tance the parallel load capacitance presented to the crystal is 9pf as determined by the following equation: this is the value load capacitance that should be us ed when selecting a crysta l and determining the actual frequency of operation of the crystal oscillator circuit. figure 3-7 external cryst al oscillator circuit 3.5.2 ceramic resonator it is also possible to drive the in ternal oscillator with a ceramic re sonator, assuming the overall system design can tolerate the re duced signal integrity. in figure 3-8 , a typical ceramic resonator circuit is shown. refer to supplier?s recomm endations when selecting a ce ramic resonator and associated components. the resonator and com ponents should be mounted as clos e as possible to the extal and xtal pins. the internal 56f80x os cillator circuitry is designed to have no external load capacitors present. as shown in figure 3-7 no external load capacitors should be used. figure 3-8 connecting a ceramic resonator note: freescale recommends only two term inal ceramic resonators vs . three terminal resonators (which contain an internal bypass capacitor to ground). cl = cl1 * cl2 cl1 + cl2 + cs = + 3 = 6 + 3 = 9pf 12 * 12 12 + 12 recommended external crystal parameters: r z = 1 to 3 m f c = 8mhz (optimized for 8mhz) extal xtal r z f c recommended ceramic resonator parameters: r z = 1 to 3 m f c = 8mhz (optimized for 8mhz) extal xtal r z f c
external clock operation 56f801 technical data, rev. 16 freescale semiconductor 25 3.5.3 external clock source the recommended method of connecting an external clock is given in figure 3-9 . the external clock source is connected to xtal and the extal pin is grounded. figure 3-9 connecting an external clock signal figure 3-10 external clock timing 3.5.4 use of on-chip re laxation oscillator an internal relaxation osci llator can supply the refere nce frequency when an exte rnal frequency source or crystal are not used. during a 56f801 boot or reset sequence, the relaxation oscillator is enabled by default, and the precs bit in the pllcr word is set to 0 ( section 3.5 ). if an external osci llator is connected, the relaxation oscillator can be desele cted instead by setting the precs bit in the pllcr to 1. when this occurs, the precss bit in the pllsr (pre scaler clock select stat us register) data word also sets to 1. if a changeover between internal and exte rnal oscillators is required at startup, internal device circuits table 3-8 external clock op eration timing requirements 3 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6 v, t a = ?40 to +85 c characteristic symbol min typ max unit frequency of operation (external clock driver) 1 1. see figure 3-9 for details on using the recommended co nnection of an external clock driver. f osc 0? 80 2 2. may not exceed 60mhz for the DSP56F801fa60 device. 3. the high or low pulse width must be no smaller than 6.25ns or the chip will not function. 4. parameters listed are guaranteed by design. mhz clock pulse width 3, 4 t pw 6.25 ? ? ns 56f801 xtal extal external clock v ss external clock v ih v il note: the midpoint is v il + (v ih ? v il )/2. 90% 50% 10% 90% 50% 10% t pw t pw
56f801 technical data, rev. 16 26 freescale semiconductor compensate for any asynchronous transi tions between the two clock signals so that no glitch es occur in the resulting master clock to th e chip. when changing clocks , the user must ensure that the clock source is not switched until the desired cl ock is enabled and stable. to compensate for variances in th e device manufacturing process, the ac curacy of the relaxation oscillator can be incrementally adjusted to within 0. 25% of 8mhz by trimming an inte rnal capacitor. bits 0-7 of the iosctl (internal oscillator contro l) word allow the user to set in an additional offset (trim) to this preset value to increase or decrea se capacitance. the default value of this trim is 128 units, making the power-up default capacito r size 432 units. each unit added or deleted changes the output frequency by about 0.2%, allowing incremental adjustment until the desired frequency accuracy is achieved. table 3-9 relaxation osci llator characteristics operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6 v, t a = ?40 to +85 c characteristic symbol min typ max unit frequency accuracy 1 1. over full temperature range. f?+ 2+ 5% frequency drift over temp f/ t?+ 0.1 ? %/ o c frequency drift over supply f/ v? 0.1 ? %/v trim accuracy f t ?+ 0.25 ? %
external clock operation 56f801 technical data, rev. 16 freescale semiconductor 27 figure 3-11 typical rel axation oscillator fre quency vs. temperature (trimmed to 8mhz @ 25 o c) figure 3-12 typical relaxat ion oscillator frequen cy vs. trim value @ 25 o c 8.0 7.8 8.1 8.2 7.7 7.9 7.6 75 55 -40 35 -25 15 -5 85 temperature ( o c) output frequency 0 10 2030405060708090a0b0c0d0e0f0 5 6 7 8 9 10 11
56f801 technical data, rev. 16 28 freescale semiconductor 3.5.5 phase locked loop timing table 3-10 pll timing operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6 v, t a = ?40 to +85 c characteristic symbol min typ max unit external reference cryst al frequency for the pll 1 1. an externally supplied reference cl ock should be as free as possible from any phase jitter for the pll to work correctly. the pll is optimized for 8mhz input crystal. 2. zclk may not exceed 80mhz. for additional information on zclk and f out /2, please refer to the occs chapter in the user manual. zclk = f op 3. will not exceed 60mhz for the DSP56F801fa60 device. 4. this is the minimum time required after the pll setup is changed to ensure reliable operation. f osc 4810mhz pll output frequency 2 f out /2 40 ? 80 3 mhz pll stabilization time 4 0 o to +85 o c t plls ?10?ms pll stabilization time 4 -40 o to 0 o c t plls ? 100 200 ms
reset, stop, wait, mode select, and interrupt timing 56f801 technical data, rev. 16 freescale semiconductor 29 3.6 reset, stop, wait, mode select, and interrupt timing table 3-11 reset, stop, wait, mode select, and interrupt timing 1, 5 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6 v, t a = ?40 to +85 c, c l 50pf 1. in the formulas, t = clock cycle. for an operating frequency of 80mhz, t = 12.5ns. characteristic symbol min max unit see reset assertion to address, data and control signals high impedance t raz ?21ns figure 3-13 minimum reset assertion duration 2 omr bit 6 = 0 omr bit 6 = 1 2. circuit stabilization delay is required during reset when using an external cloc k or crystal oscillator in two cases: ? after power-on reset ? when recovering from stop state t ra 275,000t 128t ? ? ns ns figure 3-13 reset de-assertion to first external address output t rda 33t 34t ns figure 3-13 edge-sensitive interrupt request width t irw 1.5t ? ns figure 3-14 irqa , irqb assertion to external data memory access out valid, caused by first instruction execution in the interrupt service routine t idm 15t ? ns figure 3-15 irqa , irqb assertion to general purpose output valid, caused by first instruction execution in the interrupt service routine t ig 16t ? ns figure 3-15 irqa low to first valid interrupt vector address out recovery from wait state 3 3. the minimum is specified for the duration of an edge-sensitive irqa interrupt required to recover from the stop state. this i s not the minimum required so that the irqa interrupt is accepted. t iri 13t ? ns figure 3-16 irqa width assertion to recover from stop state 4 4. the interrupt instruction fetch is visible on the pins only in mode 3. 5. parameters listed are guaranteed by design. t iw 2t ? ns figure 3-17 delay from irqa assertion to fetch of first instruction (exiting stop) omr bit 6 = 0 omr bit 6 = 1 t if ? ? 275,000t 12t ns ns figure 3-17 duration for level sensitive irqa assertion to cause the fetch of first irqa interrupt instruction (exiting stop) omr bit 6 = 0 omr bit 6 = 1 t irq ? ? 275,000t 12t ns ns figure 3-18 delay from level sensitive irqa assertion to first interrupt vector address out valid (exiting stop) omr bit 6 = 0 omr bit 6 = 1 t ii ? ? 275,000t 12t ns ns figure 3-18
56f801 technical data, rev. 16 30 freescale semiconductor figure 3-13 asynchronous reset timing figure 3-14 external interrupt ti ming (negative-edge-sensitive) figure 3-15 external level-s ensitive interrupt timing first fetch a0?a15, d0?d15 ps , ds , rd , wr reset first fetch t raz t ra t rda irqa , irqb t irw a0?a15, ps , ds , rd , wr irqa , irqb first interrupt instruction execution a) first interrupt instruction execution general purpose i/o pin irqa , irqb b) general purpose i/o t idm t ig
reset, stop, wait, mode select, and interrupt timing 56f801 technical data, rev. 16 freescale semiconductor 31 figure 3-16 interrupt fr om wait state timing figure 3-17 recovery from stop state using asynchronous interrupt timing figure 3-18 recovery from stop state using irqa interrupt service instruction fetch irqa , irqb first interrupt vector a0?a15, ps , ds , rd , wr t iri not irqa interrupt vector irqa a0?a15, ps , ds , rd , wr first instruction fetch t iw t if instruction fetch irqa a0?a15 ps , ds , rd , wr first irqa interrupt t irq t ii
56f801 technical data, rev. 16 32 freescale semiconductor 3.7 serial peripheral interface (spi) timing table 3-12 spi timing 1 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6 v, t a = ?40 to +85 c, c l 50pf 1. parameters listed are guaranteed by design. characteristic symbol min max unit see figure cycle time master slave t c 50 25 ? ? ns ns figures 3-19 , 3-20 , 3-21 , 3-22 enable lead time master slave t eld ? 25 ? ? ns ns figure 3-22 enable lag time master slave t elg ? 100 ? ? ns ns figure 3-22 clock (sck) high time master slave t ch 17.6 12.5 ? ? ns ns figures 3-19 , 3-20 , 3-21 , 3-22 clock (sck) low time master slave t cl 24.1 25 ? ? ns ns figures 3-19 , 3-20 , 3-21 , 3-22 data setup time required for inputs master slave t ds 20 0 ? ? ns ns figures 3-19 , 3-20 , 3-21 , 3-22 data hold time required for inputs master slave t dh 0 2 ? ? ns ns figures 3-19 , 3-20 , 3-21 , 3-22 access time (time to data active from high-impedance state) slave t a 4.8 15 ns figure 3-22 disable time (hold time to high-impedance state) slave t d 3.7 15.2 ns figure 3-22 data valid for outputs master slave (after enable edge) t dv ? ? 4.5 20.4 ns ns figures 3-19 , 3-20 , 3-21 , 3-22 data invalid master slave t di 0 0 ? ? ns ns figures 3-19 , 3-20 , 3-21 , 3-22 rise time master slave t r ? ? 11.5 10.0 ns ns figures 3-19 , 3-20 , 3-21 , 3-22 fall time master slave t f ? ? 9.7 9.0 ns ns figures 3-19 , 3-20 , 3-21 , 3-22
serial peripheral interface (spi) timing 56f801 technical data, rev. 16 freescale semiconductor 33 figure 3-19 spi master timing (cpha = 0) figure 3-20 spi master timing (cpha = 1) sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14?1 lsb in master msb out bits 14?1 master lsb out ss (input) ss is held high on master t f t r t di (ref) t dv t di t ds t dh t ch t cl t ch t f t f t r t r t cl t c sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14?1 lsb in master msb out bits 14? 1 master lsb out ss (input) ss is held high on master t c t cl t cl t ch t ch t f t f t r t r t ds t dh t dv t di t r t f t dv (ref)
56f801 technical data, rev. 16 34 freescale semiconductor figure 3-21 spi slave timing (cpha = 0) figure 3-22 spi slave timing (cpha = 1) sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14?1 msb in bits 14?1 lsb in ss (input) slave lsb out t c t cl t f t elg t r t ds t eld t ch t cl t a t ch t r t f t d t di t dv t dh t di sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14?1 msb in bits 14?1 lsb in ss (input) slave lsb out t di t d t r t dv t dh t f t ds t elg t f t r t ch t dv t a t eld t cl t cl t ch t c
quad timer timing 56f801 technical data, rev. 16 freescale semiconductor 35 3.8 quad timer timing figure 3-23 timer timing 3.9 serial communicati on interface (sci) timing table 3-13 timer timing 1, 2 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6 v, t a = ?40 to +85 c, c l 50pf 1. in the formulas listed, t = clock cycle. for 80mhz operation, t = 12.5ns. 2. parameters listed are guaranteed by design. characteristic symbol min max unit timer input period p in 4t+6 ? ns timer input high/low period p inhl 2t+3 ? ns timer output period p out 2t ? ns timer output high/low period p outhl 1t ? ns table 3-14 sci timing 4 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6 v, t a = ?40 to +85 c, c l 50pf characteristic symbol min max unit baud rate 1 1. f max is the frequency of operation of the system clock in mhz. br ? (f max *2.5)/(80) mbps rxd 2 pulse width 2. the rxd pin in sci0 is named rxd0 and the rxd pin in sci1 is named rxd1. rxd pw 0.965/br 1.04/br ns txd 3 pulse width 3. the txd pin in sci0 is named txd0 and the txd pin in sci1 is named txd1. 4. parameters listed are guaranteed by design. txd pw 0.965/br 1.04/br ns timer inputs timer outputs p outhl p outhl p out p in p inhl p inhl
56f801 technical data, rev. 16 36 freescale semiconductor figure 3-24 rxd pulse width figure 3-25 txd pulse width 3.10 analog-to-digital c onverter (adc) characteristics table 3-15 adc characteristics characteristic symbol min typ max unit adc input voltages v adcin 0 1 ? v ref 2 v resolution r es 12 ? 12 bits integral non-linearity 3 inl ? +/- 4 +/- 5 lsb 4 differential non-linear ity dnl ? +/- 0.9 +/- 1 lsb 4 monotonicity guaranteed adc internal clock 5 f adic 0.5 ? 5 mhz conversion range r ad v ssa ?v dda v conversion time t adc ?6 ? t aic cycles 6 sample time t ads ?1 ? t aic cycles 6 input capacitance c adi ?5 ? pf 6 gain error (transfer gain) 5 e gain 1.00 1.10 1.15 ? offset voltage 5 v offset +10 +230 +325 mv rxd sci receive data pin (input) rxd pw txd sci receive data pin (input) txd pw
analog-to-digital converter (adc) characteristics 56f801 technical data, rev. 16 freescale semiconductor 37 1. parasitic capacitance due to package, pin to pi n, and pin to package base coupling. (1.8pf) 2. parasitic capacitance due to the chip bond pad, esd protection devices and signal routing. (2.04pf) 3. equivalent resistance for the esd isolation resistor and the channel select mux. (500 ohms) 4. sampling capacitor at the sample and hold circuit. capacitor 4 is normally disconnected from the input and is only connected to it at sampling time. (1pf) figure 3-26 equivalent an alog input circuit total harmonic distortion 5 thd 55 60 ? db signal-to-noise plus distortion 5 sinad 54 56 ? db effective number of bits 5 enob 8.5 9.5 ? bit spurious free dynamic range 5 sfdr 60 65 ? db bandwidth bw ? 100 ? khz adc quiescent current (both adcs) i adc ?50 ? ma v ref quiescent current (both adcs) i vref ?12 16.5 ma 1. for optimum adc performance, keep the minimum v adcin value > 250mv. inputs less than 250mv volts may convert to a digital output code of 0 or cause erroneous conversions. 2. v ref must be equal to or less than v dda - 0.3v and must be greater than 2.7v. 3. measured in 10-90% range. 4. lsb = least significant bit. 5. guaranteed by characterization. 6. t aic = 1/ f adic table 3-15 adc characteristics (continued) characteristic symbol min typ max unit 1 2 3 4 adc analog input
56f801 technical data, rev. 16 38 freescale semiconductor 3.11 jtag timing figure 3-27 test clock input timing diagram table 3-16 jtag timing 1, 3 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6 v, t a = ?40 to +85 c, c l 50pf 1. timing is both wait state and frequency dependent. for the values listed, t = clock cycle. for 80mhz operation, t = 12.5ns. characteristic symbol min max unit tck frequency of operation 2 2. tck frequency of operation must be less than 1/8 the processor rate. 3. parameters listed are guaranteed by design. f op dc 10 mhz tck cycle time t cy 100 ? ns tck clock pulse width t pw 50 ? ns tms, tdi data setup time t ds 0.4 ? ns tms, tdi data hold time t dh 1.2 ? ns tck low to tdo data valid t dv ? 26.6 ns tck low to tdo tri-state t ts ? 23.5 ns trst assertion time t trst 50 ? ns de assertion time t de 8t ? ns tck (input) v m v il v m = v il + (v ih ? v il )/2 v m v ih t pw t pw t cy
jtag timing 56f801 technical data, rev. 16 freescale semiconductor 39 figure 3-28 test access po rt timing diagram figure 3-29 trst timing diagram figure 3-30 once?debug event input data valid output data valid output data valid tck (input) tdi (input) tdo (output) tdo (output ) tdo (output) tms t dv t dv t ts t ds t dh trst (input) t trst de t de
56f801 technical data, rev. 16 40 freescale semiconductor part 4 packaging 4.1 package and pin-out information 56f801 this section contains package and pin-out informat ion for the 48-pin lqfp c onfiguration of the 56f801. figure 4-1 top view, 56f8 01 48-pin lqfp package pin 1 orientation mark tdo td1 td2 /ss miso mosi sclk txdo v ss v dd rxd0 de tcs tck tms ireqa tdi vcapc2 v ss v dd extal xtal tdo trst ana4 ana3 vref ana2 ana1 ana0 faulta0 v ss v dd v ssa v dda reset pwma5 pwma4 pwma3 pwma2 pwma1 v ss v dd vcapc1 pwma0 ana7 ana6 ana5 pin 1 3 pin 37 pin 25
package and pin-out information 56f801 56f801 technical data, rev. 16 freescale semiconductor 41 table 4-1 56f801 pin iden tification by pin number pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1 td0 13 tcs 25 reset 37 ana5 2td114tck26v dda 38 ana6 3td215tms27v ssa 39 ana7 4ss 16 ireqa 28 v dd 40 pwma0 5miso17 tdi 29 v ss 41 vcapc1 6 mosi 18 vcapc2 30 faulta0 42 v dd 7sclk19 v ss 31 ana0 43 v ss 8txd020v dd 32 ana1 44 pwma1 9v ss 21 extal 33 ana2 45 pwma2 10 v dd 22 xtal 34 vref 46 pwma3 11 rxd0 23 tdo 35 ana3 47 pwma4 12 de 24 trst 36 ana4 48 pwma5
56f801 technical data, rev. 16 42 freescale semiconductor figure 4-2 48-pin lqfp mechanical information please see www.freescale.com for the most current case outline. a a1 z 0.200 ab t-u 4x z 0.200 ac t-u 4x b b1 1 12 13 24 25 36 37 48 s1 s v v1 p ae ae t, u , z detail y detail y base metal n j f d t-u m 0.080 z ac section ae-ae ad g 0.080 ac m top & bottom l w k aa e c h 0.250 r 9 detail ad notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeter. 3. datum plane ab is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums t, u, and z to be determined at datum plane ab. 5. dimensions s and v to be determined at seating plane ac. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 per side. dimensions a and b do include mold mismatch and are determined at datum plane ab. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.350. 8. minimum solder plate thickness shall be 0.0076. 9. exact shape of each corner is optional. case 932-03 issue f t u z ab ac gauge plane dim a min max 7.000 bsc millimeters a1 3.500 bsc b 7.000 bsc b1 3.500 bsc c 1.400 1.600 d 0.170 0.270 e 1.350 1.450 f 0.170 0.230 g 0.500 bsc h 0.050 0.150 j 0.090 0.200 k 0.500 0.700 m 12 ref n 0.090 0.160 p 0.250 bsc l 0 7 r 0.150 0.250 s 9.000 bsc s1 4.500 bsc v 9.000 bsc v1 4.500 bsc w 0.200 ref aa 1.000 ref
thermal design considerations 56f801 technical data, rev. 16 freescale semiconductor 43 part 5 design considerations 5.1 thermal design considerations an estimation of the chip junction temperature, t j , in c can be obtained from the equation: equation 1: where: t a = ambient temperature c r ja = package junction-to-ambie nt thermal resistance c/w p d = power dissipation in package historically, thermal resistance has been expressed as the sum of a j unction-to-case thermal resistance and a case-to-ambient thermal resistance: equation 2: where: r ja = package junction-to-ambie nt thermal resistance c/w r jc = package junction-to-case thermal resistance c/w r ca = package case-to-ambient thermal resistance c/w r jc is device-related and ca nnot be influenced by the user. the user controls the thermal environment to change the case-to-ambien t thermal resistance, r ca . for example, the user ca n change the air flow around the device, add a heat sink, change the mounting ar rangement on the printed circuit board (pcb), or otherwise change the thermal diss ipation capability of the area su rrounding the device on the pcb. this model is most useful for ceramic pa ckages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. for cera mic packages, in situations where the heat flow is split between a path to the case a nd an alternate path through the pcb, analysis of the device thermal performance may need the additional modeli ng capability of a sy stem level thermal simulation tool. the thermal performance of plastic packages is more dependent on the temperat ure of the pcb to which the package is mounted. again, if the estimations obtained from r ja do not satisfactorily answer whether the thermal performance is adequate, a sy stem level model may be appropriate. definitions: a complicating factor is the existe nce of three common definitions fo r determining the junction-to-case thermal resistance in plastic packages: ? measure the thermal resistance from the junction to th e outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. this is done to minimize temperature variation across the surface. t j t a p d r ja () + = r ja r jc r ca + =
56f801 technical data, rev. 16 44 freescale semiconductor ? measure the thermal resistance from the junction to where the leads are attached to the case. this definition is approximately equal to a junc tion to board thermal resistance. ? use the value obtained by the equation (t j ? t t )/p d where t t is the temperature of the package case determined by a thermocouple. the thermal characterization parameter is measured per jesd51-2 specification using a 40-gauge type t thermocouple epoxied to the top ce nter of the package case. the th ermocouple should be positioned so that the thermocouple junction re sts on the package. a small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. when heat sink is used, the junction temperature is determined from a ther mocouple inserted at the interface between the case of the p ackage and the interface material. a clearance slot or hole is normally required in the heat sink. minimizing the size of the clearan ce is important to mi nimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. because of the experimental difficulties with th is technique, many engine ers measure the heat si nk temperature and then back-calculate the case temperatur e using a separate measurement of the thermal resistance of the interface. from this case temperat ure, the junction temperature is de termined from th e junction-to-case thermal resistance. 5.2 electrical design considerations use the following list of considerat ions to assure correct operation: ? provide a low-impedance path from the board power supply to each v dd pin on the controller, and from the board ground to each v ss (gnd) pin. ? the minimum bypass requirement is to place 0.1 f capacitors positioned as close as possible to the package supply pins. the recommended bypass configura tion is to place one bypass capacitor on each of the ten v dd /v ss pairs, including v dda /v ssa. ceramic and tantalum capac itors tend to provide better performance tolerances. ? ensure that capacitor leads and associated prin ted circuit traces that connect to the chip v dd and v ss (gnd) pins are less than 0.5 inch per capacitor lead. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
electrical design considerations 56f801 technical data, rev. 16 freescale semiconductor 45 ? bypass the v dd and v ss layers of the pcb with approximately 100 f, preferably with a high-grade capacitor such as a tantalum capacitor. ? because the controller?s output signals have fast rise and fall times, pcb trace le ngths should be minimal. ? consider all device loads as well as parasitic capacitance due to pcb traces when calculating capacitance. this is especially critical in system s with higher capacitive loads that co uld create higher transient currents in the v dd and gnd circuits. ? take special care to minimize noise levels on the vref, v dda and v ssa pins. ? designs that utilize the trst pin for jtag port or once module functionality (such as development or debugging systems) should allow a means to assert trst whenever reset is asserted, as well as a means to assert trst independently of reset . trst must be asserted at power up for proper operation. designs that do not requir e debugging functionality, such as consumer products, trst should be tied low. ? because the flash memory is programmed through the jtag/once port, designers should provide an interface to this port to allo w in-circuit flash programming.
56f801 technical data, rev. 16 46 freescale semiconductor part 6 ordering information table 6-1 lists the pertinent information needed to pl ace an order. consult a freescale semiconductor sales office or authorized di stributor to determine availability and to order parts. *this package is rohs compliant. table 6-1 56f801 ordering information part supply voltage package type pin count ambient frequency (mhz) order number 56f801 3.0?3.6 v low profile plastic quad flat pack (lqfp) 48 80 DSP56F801fa80 56f801 3.0?3.6 v low profile plastic quad flat pack (lqfp) 48 60 DSP56F801fa60 56f801 3.0?3.6 v low profile plastic quad flat pack (lqfp) 48 80 DSP56F801fa80e* 56f801 3.0?3.6 v low profile plastic quad flat pack (lqfp) 48 60 DSP56F801fa60e*
electrical design considerations 56f801 technical data, rev. 16 freescale semiconductor 47
how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064, japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. this product incorporates superflash? technology licensed from sst. ? freescale semiconductor, inc. 2005. all rights reserved. DSP56F801 rev. 16 01/2007 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical ex perts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of their non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp .

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